1. Field of the Invention
The present invention relates to a semiconductor device and a control method of a switch transistor thereof, and particularly to a semiconductor device having a switch transistor for connecting a global power supply line and a local power supply line and a control method of the switch transistor.
2. Description of Related Art
In the semiconductor device, power consumption is increasing along with higher integration. Therefore, in a semiconductor device of recent years, circuits disposed in a chip are divided into multiple areas by circuit blocks, and the semiconductor device is controlled to partly block power supply for unused blocks. One of the circuits used for such power control is a power switching circuit. A power switching circuit includes a global power supply line provided for all the circuits disposed in the chip, a local power supply line provided to the circuits disposed in a power supply controlled area, and a switch transistor for controlling the connection state. Then, the power switching circuit controls the power supply to the circuits disposed in the area where the power supply is controlled (the area hereinafter referred to as a power supply controlled area) by turning on and off the switch transistor.
If this power switching circuit is used in a semiconductor device, when the power supply is resumed to the power supply controlled area, where the power supply is blocked, the current flowing to the power supply controlled area increases, thereby reducing the voltage of the global power supply line. On the other hand, in a semiconductor device of recent years, a power supply voltage is often specified to be low in order to achieve lower power consumption. In the semiconductor device that operates on such low power supply voltage, the range of operable power supply voltage tends to be narrow. That is, in the semiconductor device that operates on such low power supply voltage, the fluctuation range of the power supply voltage with guaranteed operation is narrow. Therefore, a voltage fluctuation induced by an operation of a power switching circuit for the low power supply voltage could cause a problem of an unstable operation of the semiconductor device. Thus the technique of preventing such fluctuation of the power supply voltage by a power switching circuit is disclosed in United States Patent Publication No. 2007/0103202 and Japanese Patent Translation Publication No. 2008-532265.
FIG. 14 is a block diagram of a power switching circuit disclosed in United States Patent Publication No. 2007/0103202. As illustrated in FIG. 14, in the power switching circuit disclosed in United States Patent Publication No. 2007/0103202, combination switching circuits 505 are connected in cascade. Then, a control signal PON is input to the combination switching circuit 505 which is disposed first. The control signal PON is propagated in the cascade connected combination switching circuits 505 and returns back at the combination switch 505, which is disposed to the end. The returned control signal PON (the returned control signal hereinafter referred to as PGOOD) is propagated in the cascade connected combination switching circuits 505 again, and output as a control signal PGOOD from the first combination switching circuit 505.
Further, FIG. 15 is a circuit diagram of the combination switching circuit 505. As illustrated in FIG. 15, the combination switching circuit 505 includes inverted buffer circuits 615, 617, 620, and 622, a precharge switch 605, and a header switch 610. The combination switching circuits 505 propagate the control signal PON via the inverted buffer circuits 615 and 617. Then, the precharge switch 605 is turned on by an output from the inverted buffer circuit 615. The combination switching circuits 505 propagate the control signal PGOOD via the inverted buffer circuits 620 and 622. Then, the header switch 610 is turned on by an output from the inverted buffer circuit 620. Further, the precharge switch 605 and the header switch 610 are connected in parallel between a global power supply line VDDC and a local power supply line VDD. The size of the precharge switch 605 is smaller than the header switch 610.
United States Patent Publication No. 2007/0103202 discloses that the precharge switches 605 are conducted sequentially in response to an input of the control signal PON, and then the header switches 610 are conducted sequentially. By controlling the precharge switches 605 and the header switches 610 in this way, the current supply to the local power supply line VDD is controlled at the first stage of the current supply. Then, after all the precharge switches 605 are conducted, the header switches 610 start supplying the power. By performing such control, the maximum current value flowing from the global power supply line VDDC to the local power supply line VDD can be suppressed. Further, the voltage drop of the global power supply line VDDC can be suppressed by controlling the maximum current value.
FIG. 16 is a block diagram of a distributed current supply switching circuit disclosed in Published Japanese Translation of PCT International Publication for Patent Application, No. 2008-532265. A distributed current supply switching circuit controls the current supply state to domain circuit areas 120, 128, and 130 using multiple current supply switches 131 to 139. The conducting state of the multiple current supply switches 131 to 139 is controlled by a control circuit 110. Further, the current supply switches 131 to 139 are provided between a global supply bus GGND and a local supply bus LGND. In the distributed current supply switching circuit, if a current is supplied to the domain circuit areas 120, 128, and 130, an enable signal EN1 output from the control circuit 110 is asserted to turn on the current supply switch 131. After that, an enable signal EN2 output from the control circuit 110 is asserted to sequentially turn on the current supply switches 132 to 139. This prevents from supplying a current to the drain circuit areas 120, 128, and 130 rapidly, and also from reducing the power of the global bus (for example GPWR).